Allegro PSpice Simulator
4.3
7

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The CadenceAllegroPSpiceSimulator provides complete pre- and post-layout testing for analog and mixed-signal designs with powerful simulation, debugging, design, and analysis utilities. The Allegro PSpice Simulator includes Cadence PSpice technology at the core, providing fast and accurate simulations. This advanced analysis package includes utilities for sensitivity analysis, goal-based multi-parameter optimization, component stress and reliability analysis, and Monte Carlo analysis for yield estimation. The parametric plotter analyzes interdependence among parameters and converts simulation data into meaningful results. When combined with Allegro Design Entry HDL, the schematics drawn in Allegro PSpice Simulator can also drive PCB layout, significantly reducing design time and eliminating redrawing errors. It includes a large library of known models and behavioral modeling techniques that make refining the analog/digital interface a straightforward task.
Developer
Cadence Design Systems
HQ Location
San Jose, California
Year Founded
1988
Number of Employees
8,830
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